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Lattice Semiconductor
10Gb Ethernet XGXS IP Core User’s Guide
EB
(for 4 bytes)
F4
(for 4 bytes)
AB
(for 4 bytes)
B5
(for 160 bytes)
EB
(for 4 bytes)
F4
(for 4 bytes)
EB
(for 4 bytes)
F4
(for 4 bytes)
EB
(for 4 bytes)
F4
(for 4 bytes)
EB
(for 4 bytes)
F4
(for 4 bytes)
7E
(for 528 bytes)
F4
(for 4 bytes)
EB
(for 4 bytes)
F4
(for 4 bytes)
EB
(for 4 bytes)
F4
(for 4 bytes)
EB
(for 4 bytes)
F4
(for 4 bytes)
AB
(for 4 bytes)
B5
(for 160 bytes)
EB
(for 4 bytes)
F4
(for 4 bytes)
EB
(for 4 bytes)
F4
(for 4 bytes)
EB
(for 4 bytes)
F4
(for 4 bytes)
EB
(for 4 bytes)
F4
(for 4 bytes)
CRC :
BD 9F 1E AB
IPG : (same as CRPAT)
Loopback Con ? guration
The XGXS IP solution supports three loopback capabilities as shown in Figure 9. Two of the loopbacks are imple-
mented in the IP resident in the programmable core and one is implemented in the ORT82G5 embedded core. All
of these loopbacks are controllable via the MDIO interface.
The XGXS loopback is implemented in the programmable core and loops back receive XAUI data to the transmit
XAUI interface. The XGXS loopback only works when the XAUI transmit and receive clocks are synchronized.
The XGMII loopback is implemented in the programmable core and loops back receive XGMII TX data to the
receive XGMII interface. The XGMII loopback only works when the XGMII transmit and receive clocks are synchro-
nized.
Note that the XGMII and XAUI loopbacks can operate simultaneously.
The XAUI loopback is implemented in the ORT82G5 embedded core and loops back transmit XGMII data in the
receive direction. Please refer to the ORT82G5 data sheet for additional information about this loopback capability.
13
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